Industry-leading clock buffer family features new devices

Skyworks has significantly expanded its SKY535xx family of clock fanout buffers with nine new devices that extend the family’s capabilities across a wider range of data centre, wireless network, and PCIe Gen 7 applications. The new SKY535x2/x3 devices include an I2C interface, allowing differentiated features that include dual 1:n buffer mode, individual output enable control, and additional selectable output format options that include 800mV LVDS and HCSL with programmable swing.

The expanded family offers scalable, low-jitter clock buffer solutions that simplify design and enhance signal integrity across diverse platforms, from cost-optimised designs to high-performance applications.

The new additions to the family include:

• SKY53511, a low-power, DC to 250MHz ultra-low additive jitter (50fs RMS) clock fanout buffer featuring dual any-format inputs and 10 or 20 LVCMOS outputs.
• SKY53581, a low-power, DC to 250MHz ultra-low additive jitter (50fs RMS) clock fanout buffer featuring dual any-format inputs and eight or 16 LVCMOS outputs.
• SKY53541, a low power, DC to 250MHz ultra-low additive jitter (50fs RMS) clock fanout buffer featuring dual any-format inputs four or eight LVCMOS outputs.
• SKY53512 (10 outputs), SKY53582 (eight outputs), and SKY53542 (four outputs) are low-power, DC to 800MHz, ultra-low additive jitter (37fs RMS 12kHz-20MHz) clock fanout buffers featuring dual any-format inputs and 10 HCSL outputs. The devices feature an I2C interface for in-system programming, can be operated in a dual 1:n configuration, include individual output enable, and are PCIe Gen1/2/3/4/5/6/7 compliant (3fs RMS PCIe Gen7).
• SKY53513 (10 differential outputs or 20 LVCMOS outputs), SKY53583 (eight differential outputs or 16 LVCMOS outputs), and SKY53543 (four differential outputs or eight LVCMOS outputs) are low-power, DC to 3.1GHz, ultra-low additive jitter (35fs RMS 12kHz-20MHz) clock fanout buffers featuring dual any-format inputs. The devices feature an I2C interface for in-system programming, can be operated in a dual 1:n configuration, include individual output enable, and are PCIe Gen1/2/3/4/5/6/7 compliant (3fs RMS PCIe Gen7).

The devices are suited for pairing with the company’s Si551x Network Synchronizers, SKY63104/5/6 family of Jitter Attenuating Clocks and SKY62101 Ultra-Low Jitter Clock Generators to deliver complete clock tree solutions that meet the demanding requirements of next-generation 6G wireless infrastructure, 800G/1600G networking infrastructure, and AI data centre applications that utilise 112G/224 PAM4 SerDes technology.

See the products at embedded world 2026, on Stand 332, Hall 4A, during 10-12 March 2026.